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Not "for some reason"; I didn't see it as relevant. If anything, it being a PII-lite with overclocking disabled makes it seem like a worse option? What am I missing here?


> What am I missing here?

The whole point, really. Sorry, but you are.

In the Pentium / PII era, CPU speed was the product of 2 factors: front side bus speed and clock multiplier.

The original P5 and the 2nd gen P54 ran at FSB speed: 60 MHz or 66 MHz.

The later Pentiums ran at an integer multiple:

Pentium 120 = 60 MHz * 2 P 133 = 66 * 2

The PII ran at larger multipliers. I bought a PII 450 MHz on a Gigabyte motherboard that fit in my Baby-AT case, rather than the then-common ATX case.

450 = 100 MHz FSB * 4.5

That cost.

Slower PIIs had a much slower 66 MHz FSB.

PII 300 = 66 * 4.5

The Celeron had a locked multiplier but you could change the FSB.

So, take a 300 MHz chip (running at a locked 4.5x the FSB) but put it on a much faster 100 MHz FSB at the same multiplier and you got a 450 MHz chip, and because it had a much smaller but on-die L2 cache, it was more likely to be stable.

These Celerons came on a Slot 1 convertor and that needed to be modified to enable SMP operation.

Pics:

https://www.vogonswiki.com/index.php/Intel_Celeron_300A

The famous BP6 motherboard ignored that setting and forced the uniprocessor-only Celeron to run in dual processor and overclocked it as well.

So for 2 budget sub-£150 CPUs, rated for 300 MHz on a sluggish 66MHz FSB and one CPU only, you got a dual-processor 100MHz FSB machine with the raw single-core performance of something like a £500 processor.

I never had one but you bet I heard about them and strongly considered it.


IIRC even with a locked multiplier you could overclock the CPU by increasing the base (fsb) frequency. So you would change the fsb freq from 66 to 100 MHz and this way get a 450 MHz CPU from a 300MHz one.


On the Slot 1 version of that processor you could disable the multiplier lock by cutting one of the pins on the slot.


What CPU had double the performance of a (top-of-the-line) PII CPU at the time?




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