Objects at the top of the screen are drawn after the mid-screen interrupt. Objects at the bottom of the screen are drawn after the end-screen interrupt. Thus the code and hardware work on different halves of the screen.
I'm wondering what the mechanism is here to avoid bus contention between the video circuit and the CPU both accessing the VRAM at the same time.
Might be evident from studying the schematic I would suppose...
“Space Invaders uses a simple display format where bytes are read from memory in order via an address counter, and shifted out via a shift register. Timing is controlled by discrete hardware.
The video hardware has priority over the CPU. When it needs to read a byte it asserts the 8080's READY signal, giving it exclusive access to the memory bus. This can be seen on the schematic (https://www.robotron-2084.co.uk/taito/documents/space-invade...) at 5F.
This technique has the advantage of the 8080 not having to be synchronized with the display hardware at all.”
Hardware sprite systems such as the Atari 2600 did not have any VRAM.
The 2600 had 128 bytes of RAM. It supported a small number of fixed sprites. These were implemented by setting the X and Y coordinates in registers; as the scan-out of pixels passed that point, it would switch to drawing in the sprite color if a pixel was present at the bit position in the sprite.
It was possible to count how far down the screen the scan-out had got and re-use a sprite that had already been used above, to get more than the allowed number of sprites.
See the book Racing the beam for a lot more detail.
Edit: however this WAS a VRAM system. Seems to have added a dedicated shift helper but is still using blitting to VRAM. See "game timing" section of OP page.
RAM was too expensive to have two full frame buffers with page flipping. So they resorted to timing tricks.
Many times the RAM was dual ported (CPU writes while video hardware reads).
Other times they'd do clever clock tricks... for example, using 10 MHz capable RAM, generate a 10 MHz clock, and divide it down to two different 5 Mhz. One 5MHz clock is sync'd to the rising edge of 10 MHz, the other is sync'd to the falling edge. Sort of "interleaving" the two 5 MHz clocks. Total clock rate is 10 MHz, but the two 5MHz hardware circuits are out of phase and don't interfere with each other.
Later on, as RAM prices fell and double buffered images became economically possible in arcade machines, true page flipping started getting used, they would simply isolate the CPU and video buses from each other as the frame buffer was flipped. I know this is how things worked on I, Robot (1984)... this technique could have been used earlier but not much as not many games had real frame buffers at the time.
I'm wondering what the mechanism is here to avoid bus contention between the video circuit and the CPU both accessing the VRAM at the same time.
Might be evident from studying the schematic I would suppose...