Perhaps if it's possible to generate a RISC-V CPU in 5 hours, it's also possible to generate a JIT for RISC-V with a similar approach?
https://news.ycombinator.com/item?id=36566578
"Show HN: Tetris, but the blocks are ARM instructions that execute in the browser" (2023)
https://news.ycombinator.com/item?id=37086102 ; emu86 supports WASM, MIPS, RISC-V but not yet ARM64/Aarch64
Is there a "Record and replay" or a "Time-travel debugger" at the emulator level or does e.g. rr just work because Cartesi Machine is a complete syscall emulator?
"Show HN: Tetris, but the blocks are ARM instructions that execute in the browser" (2023) https://news.ycombinator.com/item?id=37086102 ; emu86 supports WASM, MIPS, RISC-V but not yet ARM64/Aarch64
Is there a "Record and replay" or a "Time-travel debugger" at the emulator level or does e.g. rr just work because Cartesi Machine is a complete syscall emulator?