First-generation ESP32 has an exceptionally weird low-power core. Retroactively, espressif called this "FSM ULP". For example, among other weirdness, this core has only one way to write memory that:

- writes only 32-bit words;

- only at 32-bit-aligned addresses;

- user program only controls lower 16 bits of the word;

- upper 16 bits are written with, basically, garbage (part of program counter).

Second-generation, ESP32-S2 is supposed to have a regular RISC-V low-power CPU core, in addition to the FSM.

That sounds like an incredible engineering war story. I guess it was done to somehow cut down RAM access? Or a bug in the registers?

RP2040's PIO is more like TI's [PRU] than ESP32's FSM ULP.

All 3 are specialized "secondary" processor cores, but PIO & PRU are fast (faster than main CPU for bit-banged IO), where ULP is much slower (but low-power).

[PRU] https://beagleboard.org/pru