Not really. E.g. the AMD ZEN+ moved to a 12nm process but kept both transistor count and die size constant. They instead used the headroom to space features out and improve cooling.

I think the HDL guys were running around with their hair on fire for Spectre bugs, hence why it was a straight transistor shrink with next to no logic changes. It's previously unheard of to not take advantage of a process shrink with logic changes; so much of your logic decisions are ultimately rooted in the process node.

You could still specify the maximum possible transistor density for the process. It doesn't mean a concrete design actually has to use it. Or make it an SRAM bit, because caches take up the bulk of the area anyway.

Pretty much equivalent to SRAM cell density, which you can measure under a microscope.

Speaking of SRAM, it's interesting how much effort is devoted to keeping the logic busy so they don't have to spend chip area on cache.

It's a useful number but its not the whole story. Fitting more transistors into a given area lets you put more chips on a wafer which is good economically. And it correlates with performance but, for example, Intel has traditionally accepted more restrictive design rules in exchange for more performant transistors and that has hurt their effective transistor density even if their individual transistors have been fast.

It gives you a bound on the areal density of the transistors, which correlates with their switching and power performance.